1. Field of the Invention
The present invention relates to a driving circuit of a liquid crystal display (LCD) device, and more particularly, to a bi-directional driving circuit of a LCD panel that enables a bi-directional driving regardless of the number of stages.
2. Discussion of the Related Art
In general, a LCD device commonly includes a driving circuit in an LCD panel, such as a gate driving integrated circuit (IC) and a data driving IC. Also, the LCD device has a fixed driving direction, so that system makers sometimes require various panels.
FIG. 1 is a circuit diagram of a liquid crystal display (LCD) panel according to the related art. In FIG. 1, a polysilicon thin film transistor liquid crystal display (TFT LCD) panel includes a pixel array, a plurality of first shift registers 11, a plurality of first buffers 12, a plurality of second shift registers 13, and a plurality of second buffers 14. In particular, the pixel array has a plurality of gate lines G1–Gm crossing a plurality of data lines D1–Dn, such that the first shift registers 11 and buffers 12 supply scan signals GCLK and GSTART to each of the plurality of gate lines G1–Gm, and the second shift registers 13 and buffers 14 supply other scan signals DCLK and DSTART to the plurality of data lines D1–Dn.
In addition, the plurality of data lines D1–Dn are divided into a k-number of blocks, such that there are a k-number of second shift registers 13 and buffers 14, and each of the k-number of second shift registers 13 and buffers 14 supplies scan signals through one of lines d1–dk to each of the k-number of blocks of data lines D1–Dn. Moreover, the LCD panel includes a signal bus 15 having a plurality of signal lines s1–sn for transmitting video signals output from a digital-to-analog converter of a data driving circuit (not shown) to each of the plurality of data lines D1–Dn, and a plurality of switching elements 16 for sequentially supplying video signals of the signal lines s1–sn to each of the k-number of blocks of the data lines D1–Dn based on signals output from the second shift registers 13 and buffers 14.
Thus, by dividing the data lines D1–Dn into blocks, the driving circuit has a reduced number of contact lines between an external circuit and the panel. However, in the block arrangement of the data lines D1–Dn, the gate lines and the data lines are sequentially driven by the shift registers to display limited picture images. For example, since the shift registers shift in a fixed direction, the driving circuit then does not have freedom in a driving direction as required by some system makers, thereby requiring various panels.
FIG. 2 is a circuit diagram of a shift register of a LCD panel according to the related art. In FIG. 2, a start pulse VST, four clock signals CLK1–CLK4 each having different phases, and power source voltages Vdd and Vss are input to a shift register. In addition, the shift register includes eight blocks of transistors each having similar structures, such that the power source voltages Vdd and Vss are similarly supplied to each of the eight blocks, but the four clock signals CLK1–CLK4 are differently supplied to each of the eight blocks.
In particular, each of the eight blocks of transistors includes first, second, third, fourth, fifth, sixth, and seventh p-MOS transistors TFT1–TFT7. The first transistor TFT1 has drain and gate terminals connected to either a VST terminal to which the start pulse VST is supplied to, or an output terminal of the previous block. Thus, in the first block, the drain and gate terminals of the first transistor TFT1 are connected to the VST terminal, and in the second block, the drain and gate terminals of the first transistor TFT1 are connected to a first output terminal Output1 of the first block.
In addition, the second transistor TFT2 has a drain terminal connected to a source terminal of the first transistor TFT1, and a gate terminal to which one of the four clock signals CLK1–CLK4 is supplied. For example, in the first block, the fourth clock signal CLK4 is supplied, and in the second block, the first clock signal CLK1 is supplied. The third transistor TFT3 has a source terminal connected to a source terminal of the second transistor TFT2, and a drain terminal connected to a Vss terminal to which the power source voltage Vss is supplied to. The fourth transistor TFT4 has a drain terminal connected to a Vdd terminal to which the power source voltage Vdd is supplied to, a gate terminal to which another one of the four clock signals CLK1–CLK4 is supplied, and a source terminal connected to a gate terminal of the third transistor TFT3. For example, in the first block, the third clock signal CLK3 is supplied, and in the second block, the fourth clock signal CLK4 is supplied.
Furthermore, the fifth transistor TFT5 has a drain terminal connected to the gate terminal of the third transistor TFT3 and the source terminal of the fourth transistor TFT4, and a source terminal connected to the Vss terminal. The fifth transistor TFT5 also has a gate terminal connected to either the VST terminal or the output terminal of the previous block. Thus, in the first block, the gate terminal of the fifth transistor TFT5 is connected to the VST terminal, and in the second block, the gate terminal of the fifth transistor TFT5 is connected to the first output terminal, Output1.
Moreover, the sixth transistor TFT6 has a drain terminal to which one of the four clock signals CLK1–CLK4 is supplied, and a gate terminal connected to a node Q that is also connected to the source terminals of the second and third transistors TFT2 and TFT3. For example, in the first block, the first clock signal CLK1 is supplied, and in the second block, the second clock signal CLK2 is supplied. The sixth transistor TFT6 further has a source terminal connected to a corresponding output terminal. For example, in the first block, the source terminal of the sixth transistor TFT6 is connected to the first output terminal Output1, and in the second block, the source terminal of the sixth transistor TFT6 is connected to the second output terminal Output2. The seventh transistor TFT7 has a drain terminal connected to the corresponding output terminal, a source terminal connected to the Vss terminal, and a gate terminal connected to another node QB that is also connected to the gate terminal of the third transistor TFT3, the drain terminal of the fifth terminal TFT5, and the source terminal of the fourth transistor TFT4.
Furthermore, a first capacitor C1 connects and grounds the source terminal of the second transistor TFT2 and the drain terminal of the third transistor TFT3. At the node Q, a second capacitor connects the gate terminal of the sixth transistor TFT6 to the Vss terminal. A third capacitor connects the gate and the source terminals of the sixth, transistor TFT6. At node QB, a fourth capacitor connects the gate terminal of the seventh transistor TFT7 and the Vss terminal.
In general, an output terminal of a previous block is connected to the drain and gate terminals of the first transistor TFT1 of the next block and to the gate terminal of the fifth transistor TFT5 of the next block. For example, the first output terminal Output1 is connected to the drain and gate terminals of the first transistor TFT1 of the second block and the gate terminal of the fifth transistor TFT5 of the second block. In addition, the first clock signal CLK1 is supplied to the drain terminal of the sixth transistor TFT6 in each of the first and the fifth blocks, the gate terminal of the second transistor TFT2 in each of the second and sixth blocks, and the gate terminal of the fourth transistor TFT4 in each of the third and seventh blocks. The second clock signal CLK2 is supplied to the drain terminal of the sixth transistor TFT6 in each of the second block and the sixth blocks, the gate terminal of the second transistor TFT2 in each of the third and seventh blocks, and the gate terminal of the fourth transistor TFT4 in each of the fourth and eight blocks.
Moreover, the third clock signal CLK3 is supplied to the gate terminal of the fourth transistor TFT4 in each of the first and fifth blocks, the drain terminal of the sixth transistor TFT6 in each of the third block and the seventh blocks, and the gate terminal of the second transistor TFT2 in each of the fourth and eighth blocks. The fourth clock signal CLK4 is supplied to the gate terminal of the second transistor TFT2 of each of the first and fifth blocks, the gate terminal of the fourth transistor TFT4 in each of the second and sixth blocks, and the drain terminal of the sixth transistor TFT6 in each of the fourth block and the eighth blocks.
FIG. 3 illustrates input and output waveforms of the shift register of the LCD panel of FIG. 2. In FIG. 3, the clock signals CLK1–CLK4 are sequentially LOW. For example, during a first time period, 0s–20 μs, the start pulse VST is LOW (0 V). Thus, in the first block, the first transistor TFT1 is turned ON, and the fifth transistor TFT5 is turned ON. Also, the fourth clock signal CLK4 is LOW and the second transistor TFT2 is also turned ON. Accordingly, the node Q becomes LOW, thereby turning the sixth transistor TFT6 ON. As a result, the first clock signal CLK1 is output to the first output terminal Output1. In addition, because the fifth transistor TFT5 is turned ON, the node QB is HIGH (10V), thereby turning the seventh transistor TFT7 OFF. Accordingly, the power source voltage Vss is not output to the first output terminal Output1.
During a second time period, 20μs–40 μs, the first clock signal CLK1 is LOW, which is the output of the first block, and is supplied to the drain and gate terminals of the first transistor TFT1 of the second block and the gate terminal of the fifth transistor TFT5 of the second block. Thus, in the second block, the first, second, and fifth transistors TFT1, TFT2, and TFT5 are turned ON, such that the node Q is HIGH, thereby turning the sixth transistor TFT6 ON. Accordingly, the second clock signal CLK2 is output to the second output terminal Output2. Similarly, because the fifth transistor TFT5 is turned ON, the node QB is HIGH, thereby turning the seventh transistor TFT7 OFF. Accordingly, the power source voltage Vss is not output to the second output terminal Output2.
However, the LCD panel according to the related art is disadvantageous. For example, picture images can be scanned only in an originally designed direction of the LCD panel, such that the LCD panel must generate images in the order of the first block to the last block. Accordingly, the LCD has only one fixed orientation, such that the LCD panel is not versatile and can not be flipped from a landscape orientation to a portrait type orientation.
FIG. 4 is a circuit diagram of a bi-directional shift register of an LCD panel according to the related art and U.S. patent application Ser. No. 10/082,125. In FIG. 4, a gate or data start pulse VST, four clock signals CLK1–CLK4 each having different phases, and power source voltage Vdd and Vss may be input to a shift register. In addition, the shift register may include eight blocks of transistors each having similar structures, such that power source voltages Vdd and Vss may be similarly supplied to each of the eight blocks, but the four clock signals CLK1–CLK4 may be differently supplied to each of the eight blocks.
In particular, each of the eight blocks may includes first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth p-MOS transistor TFT1–TFT9. The first transistor may have drain and gate terminals connected to either a VST input terminal to which the start pulse VST is supplied, or an output terminal of the previous block. Thus, in the first block, the drain and gate terminals of the first transistor TFT1 may be connected to the VST input terminal, and in the second block, the drain and gate terminals of the first transistor TFT1 may be connected to a first output terminal Output1.
In addition, the second transistor TFT2 may have a drain terminal connected to a source of the first transistor TFT1, and a gate terminal to which one of the four clock signals CLK1–CLK4 is supplied. For example, in the first block, the fourth clock signal CLK4 may be supplied, and in the second block, the first clock signal CLK1 may be supplied. The third transistor TFT3 may have a source terminal connected to a source of the second transistor TFT2, and a drain terminal connected to a Vss terminal to which the power source voltage Vss is supplied. The fourth transistor TFT4 may have a drain terminal connected to a Vdd terminal to which the power source voltage Vdd supplied, and a gate terminal to which another one of the four clock signals CLK1–CLK4 is supplied, and a source terminal connected to a gate terminal of the third p-MOS transistor TFT3. For example, in the first block, the third clock signal CLK3 may be supplied, and in the second block, the fourth clock signal CLK4 may be supplied.
Further, the fifth transistor TFT5 may have a drain terminal connected at a node QB to the gate terminal of the third transistor TFT3 and the source terminal of the fourth transistor TFT4, a gate terminal connected to a node Q, which is also connected to the source terminals of the second and third transistors TFT2 and TFT3, and a source terminal connected to the Vss terminal. The sixth transistor TFT6 may have a drain terminal to which one of the four clock signals CLK1–CLK4 is supplied, a gate terminal connected to the node Q, and a source terminal connected to a corresponding output terminal. For example, in the first block, the first clock signal CLK1 may be supplied, and in the second block, the second clock signal CLK2 may be supplied. In addition, in the first block, the source terminal of the sixth transistor TFT6 may be connected to the first output terminal Output1, and in the second block, the source terminal of the sixth transistor may be connected to the second output terminal Output2.
Moreover, the seventh transistor TFT7 may have a drain terminal connected to the corresponding output terminal, a gate terminal connected to the node QB, and a source terminal connected to the Vss terminal. The eighth transistor TFT8 may have drain and gate terminals connected to an output terminal of the next block, and a source terminal connected to the source terminal of the first transistor TFT1. For example, in the first block, the drain and gate terminals of the eight transistor may be connected to the second output terminal Output2. The ninth transistor TFT9 may be connected in parallel to the second transistor TFT2, such that the drain terminal of the ninth transistor TFT9 may be connected to the source terminal of the second transistor TFT2, and the source terminal of the ninth transistor TFT9 may be connected to the drain terminal of the second transistor TFT2. In addition, the ninth transistor may have a gate terminal to which one of the four clock signals CLK1–CLK4 is supplied. For example, in the first block, the second clock signal CLK2 may be supplied, and in the second block, the third clock signal CLK3 may be supplied.
Furthermore, a first capacitor may connect to and ground the source terminal of the first transistor TFT1, the drain terminal of the second transistor TFT2, and the source terminals of the eighth and ninth transistors TFT8 and TFT9. A second capacitor may connect the gate terminal of the sixth p-MOS transistor TFT6 to the Vss terminal. A third capacitor C3 may connect to the gate and source terminals of TFT6. A fourth capacitor C4 may connect the gate terminal of the seventh p-MOS transistor TFT7 to the Vss terminal. Accordingly, the first clock signal CLK1 may be supplied to the drain terminal of the sixth p-MOS transistor TFT6 in the first and fifth blocks, the gate terminal of the second p-MOS transistor TFT2 in the second and sixth blocks, the gate terminal of the fourth p-MOS transistor TFT4 in the third and seventh blocks, and the gate terminal of the ninth p-MOS transistor TFT9 in the fourth and eighth blocks. The second clock signal CLK2 may be supplied to the gate terminal of the ninth p-MOS transistor TFT9 in the first and fifth blocks, the drain terminal of the sixth p-MOS transistor TFT6 in the second and sixth blocks, the gate terminal of the second p-MOS transistor TFT2 in the third and seventh blocks, and the gate terminal of the fourth p-MOS transistor TFT4 in the fourth and eighth blocks.
Also, the third clock signal CLK3 may be supplied to the gate terminal of the fourth p-MOS transistor TFT4 in the first and fifth blocks, the gate terminal of the ninth p-MOS transistor TFT9 in the second and sixth blocks, the drain terminal of the sixth p-MOS transistor TFT6 in the third and seventh blocks, and the gate terminal of the second p-MOS transistor TFT2 in the fourth and eighth blocks. The fourth clock signal CLK4 may be supplied to the gate terminal of the second p-MOS transistor TFT2 in the first and fifth blocks, the gate terminal of the fourth p-MOS transistor TFT4 in the second and sixth blocks, the gate terminal of the ninth p-MOS transistor TFT9 in the third and seventh blocks, and the drain terminal of the sixth p-MOS transistor TFT6 in the fourth and eighth blocks.
FIG. 5 illustrates forward input and output waveforms of the shift register of the LCD panel of FIG. 4. In FIG. 5, the clock signals CLK1–CLK4 may be sequentially set LOW. For example, during a first time period, 0 s–20 μs, the start pulse VST may be set LOW (0V). Thus, in the first block in FIG. 4, the first and fifth transistors TFT1 and TFT5 may be turned ON. Also, the fourth clock signal CLK4 may be set LOW, thereby turning the second transistor TFT2 ON. Accordingly, the node Q may become LOW, thereby turning the sixth transistor TFT6 ON. As a result, the first clock signal CLK1 may be outputted to the first output terminal Output1. In addition, because the fifth transistor TFT5 may be turned ON, the node QB may be set HIGH (10V), thereby turning the seventh transistor OFF. Accordingly, the power source voltage Vss may not be outputted to the first output terminal Output1.
In addition, during a second time period, 20 μs–40 μs, the first clock signal CLK1 may be set LOW, which is the output of the first block, and may be supplied to the drain and gate terminals of the first transistor TFT1 of the second block. Thus, in the second block, the first and second transistors TFT1 and TFT2 may be turned ON, thereby turning the sixth transistor TFT6 ON. As a result, the second clock signal CLK2 may be outputted to the second output terminal Output2.
FIG. 6 illustrates backward input and output waveforms of the shift register of the LCD panel of FIG. 4. In FIG. 6, the clock signals CLK1–CLK4 may be set LOW in reverse sequence. For example, during a first period, 0 s–20 μs, the start pulse VST may be set LOW. Thus, in the first block, the first transistor TFT1 may be turned ON. Also, the fourth clock signal CLK4 may be set HIGH, thereby turning the second transistor TFT2 OFF. As a result, the sixth transistor TFT6 may be turned OFF, thereby failing to output the first clock signal CLK1 to the first output terminal Output1.
However, in the eighth block, the first transistor TFT1 and the ninth transistor TFT9 may be both turned ON. As a result, the sixth transistor TFT6 of the eighth block may be turned ON, thereby outputting the fourth clock signal CLK4 to the eight output terminal Output8.
In addition, the output signal from the eighth output terminal Output8 may be supplied to the eighth transistor TFT8 of the seventh block. Then, the fourth clock signal CLK4 may be set LOW, thereby turning the eighth and ninth transistors TFT8 and TFT9 in the seventh block ON. As a result, the sixth transistor TFT6 of the seventh block may be turned ON, thereby outputting the third clock signal CLK3 to the seventh output terminal Output7.
Accordingly, the start pulse VST may be synchronized with the first clock signal CLK1 to output the fourth to first clock signals CLK4–CLK1 in sequence, starting from the eighth block to the first block. Thus, the shift register of FIG. 4 may provide both forward and backward scanning in a LCD panel, such that the LCD panel may function in both landscape and portrait orientations. However, such LCD panel may experience image distortions when it has a number of blocks of transistors that is not a multiple of 4.
FIG. 7 is a circuit diagram of a shift register of an LCD panel having five stages of FIG. 4. In FIG. 7, a shift register may have first, second, third, fourth and fifth blocks of p-MOS transistors similar to the first-fourth blocks of transistors in FIG. 4, except the gate and drain terminals of the eighth transistor in the fifth block may be connected to the VST terminal.
FIG. 8 illustrates forward input and output waveforms of the shift register of the LCD panel of FIG. 7. In FIG. 8, the four clock signals CLK1–CLK4 may be set LOW in sequence. For example, during a first time period, 0 s–20 μs when the start pulse VST may be LOW, in the first block, the first transistor TFT1 may be ON). Also, the fourth clock signal CLK4 may be LOW, the second transistor TFT2 may be ON. As a result, the node Q may become LOW, thereby turning the sixth transistor TFT6 ON. Accordingly, the first clock signal CLK1 may be outputted to the first output terminal Output1. In addition, the node QB may become HIGH, thereby turning the seventh transistor TFT7 OFF. Accordingly, the Vss voltage may not be outputted to the first output terminal Output1.
In addition, during the first time period, the LOW-level start pulse VST may also be inputted to the gate terminal of the eighth transistor TFT8 in the fifth block. Since the fourth clock signal CLK4 may also be LOW, the second transistor TFT2 may be turned ON. As a result, the node Q may be LOW, thereby turning the sixth transistor TFT6 ON. Hence, the first clock signal CLK1 may also be outputted to the fifth output terminal Output5. Accordingly, two outputs may be erroneously generated both at the first and fifth output terminals Output1 and Output5 during about 20–40 μs.
FIG. 9 illustrates backward input and output waveforms of the shift register of the LCD panel of FIG. 7. In FIG. 9, two outputs may also erroneously generated both at the first and fifth output terminals Output1 and Output5 during about 20–40 μs.